The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a global input/output line of a data transfer path and its surrounding circuits.
In general, prior semiconductor memory devices, such as Graphic DDR SDRAM, have a quarter-bank structure as shown in FIG. 1 for high-speed operation.
More specifically, referring to FIG. 1, in the case of an 8-bank (BK0˜BK7) structure, each bank BK0˜BK7 is dividedly disposed into four regions, in which input/output pads (not shown) and repeaters 10 are disposed between quarter banks BK0˜BK7 in an upper portion and quarter banks BK0˜BK7 in a lower portion.
Global input/output lines GIO_UP_RPT, GIO_DN_RPT are connected between the input/output pads and the repeaters 10 respectively. The global input/output lines GIO_UP are connected between the quarter banks BK0˜BK7 in the upper portion and the repeaters 10 and the global input/output lines GIO_DN are connected between the quarter banks BK0˜BK7 in the lower portion and the repeaters 10.
For example, if the semiconductor memory device of FIG. 1 has 32 input/output pads (not shown), the input/output pads are connected to the repeaters 10 corresponding to each region via 16 global input/output lines GIO_UP_RPT and 16 global input/output line GIO_DN_RPT. As a result, 8 global input/output lines (for example, GIO_UP_RPT) are connected to single repeater 10.
A prior semiconductor memory device having such structure as outlined above, if the data is inputted to a certain repeater 10 via the global input/output lines GIO_UP_RPT, GIO_DN_RPT, GIO_UP, GIO_DN, the repeater 10 amplifies the input data and delivers it to a corresponding quarter bank or corresponding input/output pad.
Since the global input/output lines GIO_UP, GIO_DN connecting each quarter bank BK0˜BK7 and each repeater 10 are dividedly disposed in each quarter bank region, a length of the global input/output lines GIO_UP, GIO_DN becomes shortened. The shortening results in high speed operation and low consumption of write operation current IDD4W.
However, since each bank BK0˜BK7 is dividedly disposed in a quarter, it is necessary to have a bank control block (not shown) for each of the quarter banks BK0˜BK7. A bank control block made up of, for example, a row decoder (X-decoder), a column decoder (Y-decoder), an input/output sense amplifier, and a write driver. Therefore the additional bank control block presents disadvantages in that the size of a memory chip becomes larger and the bank control block consumes a large current.
To compensate for these disadvantages of the quarter-bank structure outline above, a conventionally proposed half-bank structure is shown in FIG. 2.
That is, referring to FIG. 2, in the case of 8-bank BK0˜BK7 structure, each bank BK0˜BK7 is dividedly disposed into 4 regions, in which 4 banks BK0˜BK3 are disposed into two upper regions of the 4 regions as half banks BK0˜BK3 and 4 banks BK4˜BK7 are disposed into two lower regions of the 4 regions as half banks BK4˜BK7.
If 32 input/output pads (not shown) are disposed between the upper half banks BK0˜BK3 and the lower half banks BK4˜BK7, the input/output pads are connected to the repeaters 20 corresponding to each region via 32 global input/output lines GIO_RTP. At this time, single repeater 20 is connected to 16 global input/output lines GIO_RPT.
Further, 16 global input/output lines GIO_COMM connecting the repeaters 20 and the half banks BK0˜BK7 are disposed between the 4 half banks BK0, BK1, BK4, BK5 and 4 half banks BK2, BK3, BK6, BK7.
As such, according to the half-bank structure of FIG. 2, the number of the divided banks is reduced by ½ as compared to the quarter-bank structure outlined above. Thus, the number of control blocks (not shown) for controlling each bank may also be reduced by ½. Therefore, advantages can be realized including the size of the memory chip becomes smaller and currents consumed by the bank control block are low.
However, the length of the global input/output line GIO_COMM connecting the half banks BK0˜BK7 and the repeaters 20 is almost doubled as compared to the global input/output lines (for example, GIO_UP, GIO_DN of FIG. 1) of the quarter-bank structure.
A problem exists however, if the length of the global input/output line GIO_COMM becomes longer, data access time can increase due to slop data carried on the global input/output line GIO_COMM.
Further, according to the prior semiconductor memory device of a half-bank structure, there is a problem in that the write operational current consumption can increase in correspondence with a length of the global input/output line GIO_COMM. For example, the write operational current consumed by the prior semiconductor memory device of a half-bank structure can almost double as compared with the quarter-bank structure.
Moreover, the prior semiconductor memory device of a half-bank structure is structured such that input/output sense amplifiers (not shown) that amplify data output by the plurality of banks BK0˜BK7, share a single global input/output line GIO_COMM. Therefore, since the global input/output line GIO_COMM can be heavily loaded due to the junction of the input/output sense amplifiers, there are problems such that the data access time can increase and simultaneously, the current consumed by the input/output sense amplifier can increase.